Reliability and Lifetime Assessment of Through-Silicon Vias Under Thermal Cycling

Reliability and Lifetime Assessment of Through-Silicon Vias Under Thermal Cycling

Citation

Viljanto, H. (2015). Reliability and Lifetime Assessment of Through-Silicon Vias Under Thermal Cycling (Master's thesis, Aalto University, School of Electrical Engineering). 

 

Brief

This master's thesis presents a study on the reliability and lifetime of copper-filled Through-Silicon Vias (TSVs) under thermal cycling by examining the effects of different design choices on reliability, performing reliability tests, and analyzing failures using techniques like FEM and Weibull analysis. 

Summary

This master’s thesis investigates the reliability of copper-filled Through-Silicon Vias (TSVs). TSVs are vertical electrical connections used in three-dimensional integrated circuits (3D ICs) to connect stacked chips. The thesis presents a literature review of TSV fabrication processes, reliability challenges, and failure mechanisms, and conducts an experimental study on the lifetime and reliability of partially copper-filled tapered blind TSVs.

The literature review covers these key aspects of TSVs:

  • Fabrication processes: The thesis outlines the steps involved in creating TSVs, including etching the vias, depositing insulation and barrier layers, and filling the vias.
  • Reliability challenges: The fabrication of TSVs presents various challenges due to the high aspect ratio of the vias. The thesis discusses how these challenges impact the quality of insulation and barrier layers, potentially leading to issues like electrical leakage.
  • Failure mechanisms: The thesis examines common failure mechanisms in TSVs, such as copper diffusion into the active silicon region, dielectric breakdown of the insulation layer, electromigration, and thermal stress.

The experimental study involved several components:

  • Thermal cycling test: Nine samples, six with 420 vias and three with 1400 vias, underwent thermal cycling tests. The tests aimed to assess the TSVs' lifetime and reliability by measuring resistance changes. A sample was marked as failed when an open circuit occurred.
  • Resistance measurements: The study recorded resistance measurements during the thermal cycling. Samples with more vias unexpectedly exhibited greater durability than those with fewer vias. Resistance increased consistently across daisy chain loops in most samples, suggesting the gradual formation and spread of defects.
  • Weibull analysis: This statistical method was employed to analyze the data from the thermal cycling test and estimate the lifetime of the TSVs. The limited sample size for chips with 1400 vias hampered the reliability of the analysis for this group. However, the analysis yielded meaningful results for the samples with 420 vias.
  • FEM simulations: Finite Element Method (FEM) simulations were utilized to model the stress distribution within the TSV structure. The simulations consistently identified the intersection of the copper and silicon dioxide layer at the bottom of the via as the most vulnerable point for failure.
  • SEM imaging: Scanning Electron Microscopy (SEM) was used to visually examine the test samples and identify failure points. The observed failures aligned with the critical areas predicted by the FEM simulations.

The findings indicate that the tested tapered annular TSVs are susceptible to crack formation and propagation, ultimately leading to failure. This vulnerability is likely associated with the specific design and fabrication processes of the tested TSVs. The thesis concludes by emphasizing the importance of further research with a larger sample size and advanced imaging techniques to gain a more comprehensive understanding of TSV failure mechanisms.

Origin: https://aaltodoc.aalto.fi/server/api/core/bitstreams/8c7673c9-c9a5-4b88-8d54-9a46a8c8fe19/content

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