Novel glass substrates for minimizing thermal stress development during electronic device packaging process
Citation
*Nomura, S., Sawamura, S., Hanawa, Y., Sakai, Y., & Hayashi, K. (2016). Novel glass substrates for minimizing thermal stress development during electronic device packaging process. , 2016, 607-617.
- CTE control
- Glass career/substrate
- Thermal stress development
- Warpage
- Si-matched CTE
- Fan-Out Wafer Level Packaging (FOWLP)
Brief
Researchers developed a novel glass substrate whose coefficient of thermal expansion (CTE) is perfectly matched with that of silicon to minimize thermal stress development during the electronic device packaging process. The sources also report on a series of glass substrates whose CTEs are finely controlled in sub-ppm order and within the range of 3.3 - 12.0 ppm/°C.
Summary
This article, published in the Proceedings of the International Symposium on Microelectronics (ISOM) in 2016, focuses on the development and importance of novel glass substrates with controlled coefficients of thermal expansion (CTE) for use in electronic device packaging.
The authors, Shuhei Nomura, Shigeki Sawamura, Yu Hanawa, Yusuke Sakai, and Kazutaka Hayashi, highlight the challenges posed by thermal stress during packaging processes due to CTE mismatches between glass and other materials like silicon. They explain that such mismatches can lead to undesirable warpage, especially in large-scale manufacturing processes.
To address this issue, the article discusses two key advancements:
- Si-CTE Matching Glass: A novel glass composition (Glass C) is introduced, exhibiting a CTE almost perfectly matched to that of silicon across a wide temperature range. This development is particularly beneficial for processes like silicon back grinding and through-glass via (TGV) technology, where direct contact between silicon and glass is required. Simulations and experimental results demonstrate that using this glass significantly minimizes warpage compared to conventional glasses.
- CTE-Tunable Glass Series: Recognizing that different packaging processes have varying CTE requirements, the authors also present a series of glass substrates with finely controlled CTEs ranging from 3.3 to 12.0 ppm/°C. This range is achieved through variations in glass composition and thermal history. This allows manufacturers to select a glass substrate with a CTE tailored to specific applications, such as Fan-Out Wafer Level Packaging (FOWLP), where CTE matching with mold compounds is critical.
The article concludes by emphasizing that these novel glass substrates with controlled CTEs offer a significant advancement in minimizing thermal stress during electronic device packaging, leading to improved product reliability and performance.